EITF20 Datorarkitektur

2012/2013 Ht2

Kursprogram

Lectures

Mondays 10-12 and Thursdays 8-10

Schedule:

• Thur 2012-11-01 E:B: Performance, Quantitative principles; HP Ch. 1 (slides)
• Mon 2012-11-05 E:1406: Instruction set architectures, ISA; HP Ch. 1.3, App. B (slides); Article:  Peter Varhol, "GPU vs. CPU Computing"
• Thur 2012-11-08 E:C: Pipelining I; HP App. A.1-A.5 (slides)
• Mon 2012-11-12 V:C: Pipelining II; HP App. A.6-A.7, Ch. 2.1-2.6, 2.9 (slides)
• Thur 2012-11-15 E:C: Pipelining III; HP Ch. 2.4-2.8,3.1-3.4 (slides) (Pipeline Summary)
• Mon 2012-11-19 E:1406: Memory systems, cache I; HP Ch 5.1, 5.3, (App. C.1-C.3) (slides)
• Thur 2012-11-22 E:C: Memory systems, cache II; HP Ch. 5.2, (App C.2-C.3) (slides)
• Thur 2012-11-29 E:C: Memory systems, virtual memory; HP App C.4, Ch. 5.5-5.6 (slides)
• (Thur 2012-12-06 E:3119: No Lecture - Question hour)
• Mon 2012-12-10 E:1406: Storage Systems, I/O; HP Ch. 6.1-6.4, 6.6-6.7 (slides)
• Thur 2012-12-13 E:C: Case studies, Special purpose processors, embedded; HP App. D (slides);
  Questions

Question hours (frågetimmar)

• Thursday 2012-12-06 10-12 in E:3119, Anders Ardö
• Tuesday 2012-12-11 10-12 in E:4115,  Michal Stala
• Thursday 2012-12-13 10-12 in E:2347A, Anders Ardö
• Friday 2012-12-14 10-12 in E:4116,  Michal Stala

Laboratories

There are 4 laboratories

Lab assignments/manual.

You need to sign up for the labs via the 'Sign up' page in the menu to the left! (Rooms E:4115, E:4116)

1. (Week 46) Pipelined processors.
2. (Week 47) Advanced pipelining.
3. (Week 48) Cache memory.
4. (Week 49) Advanced cache, tradeoffs.

Assessment

Examination through approved labs followed by a successful written examination