Acceleration of Network Protocol Processing for System-on-a-Chip
Jon Eibertzon (C01) och Sebastian Hultqvist (C01)
With increasing network speeds the processor is becoming the bottleneck in network communications. This is due to that a large part of the time the CPU is occupied by copying data and calculating checksums. This problem could be solved by moving this type of functionality from software to hardware.
The purpose of this master's project is to develop an offload engine for protocol processing for the ETRAX SoC platform, developed and used in products by Axis Communications.
This master's project is preceded by an earlier project that has investigated the possibilities of implementing and integrating such a solution, but only for TCP/IP offloading. Our task is to generalize this solution to support a wider range of protocols and to model a programmable offload engine in the hardware description language Verilog. Included in the task is also to show how efficiently the resulting device performs the offloading.
Handledare: Mikael Starvik (Axis) och Mats Cedervall (EIT)