VCD Case Sensitivity:
Verilog designs are case-sensitive, so ModelSim maintains case when it produces a VCD file. However, VHDL is not case-sensitive, so ModelSim converts all signal names to lower case when it produces a VCD file. 

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Before trying read vcd file in PrimTime:

Open the *.vcd file (which you have already generated with Questasim) and see these two lines at the very beginning of file:


$scope module <YOURTESTBENCH_NAME> $end
$scope module <DUT> $end

<YOURTESTBENCH_NAME> (without <>) is the toplevel testbench entinty name you used to create VCD file
<DUT> (without <>) is the toplevel module which testbench is testing it.

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To read vcd file in PrimeTime you should use:
read_vcd -strip_path "/YOURTESTBENC/DUT" ${SIM_OUT}/${TOP_NAME}.vcd

Make sure what you see in VCD file is exactly what you reflect in the read_vcd line in PrimeTime. difference in upper/lowe case letters may end up in 0% annotation coverage.