compile DESIGN files
compile DESIGN testbench
compile memory Behavioral model (*.v)
compile Netlist file (DESIGN.v) which is the output of synthesis

To simulate DESIGN with the SDF file (Standard Delay Format) which you got from synthesis,
use this command in modelsim terminal:

vsim -L CLOCK65LPLVT -L CORE65LPLVT -sdfmax /{DESIGN_TESTBENCH}/DUT={path to your SDF file} work.{DESIGN_TESTBENCH}

## remember to:
# Replace {DESIGN_TESTBENCH} with you testbench name
# Replace {path to your SDF file} with the path that your sdf file is located: 
# For example: /home/piraten/ma1570no/synt/outputs/TopPads.sdf