ST Microelectronics 65nm CMOS v5.8


[Nov 2021] This is now the newest version of this design kit and must be used if any
fabrication is planned for the design.

As usual the access to this PDK is restricted to the special group of Linux computers
in the radiocad cluster. Those without a local account on these machines are not
able to use this design kit.

Something about digital design and synthesis



Setup procedure

The environment is defined by a setup script which is called by the command

> source /usr/hidden/cmp/s65v58/setup


The first time this is run, the script will also copy some files that are necessary for
proper function of the design kit. Afterwards the Cadence design tool can be started by

> virtuoso &

Connect new libraries to technology cmos065 .

Using Momentum

In order to get access to the Momentum tool from Keysight the alternative
setup script "setup.mom" must be used. Remove the local ".cdsinit" file first
because a new one is required.

The substrate file with the process parameters required is located in the library
$ST65SOI/momentum_cmos065rf_7m4x0y2z/2.0.a-00/MomentumSDB/

Simulation

The Spectre simulator can be started from the schematic window by Launch > ADE L. The
environment have been defined by the startup files.

Documentation

There is also a set of maunuals which can be read by a html-browser started by the command

> firefox -no-remote $DKITROOT/doc/html/index.html

Extra Pads

There is a set of small rf-pads created by Carl. They can be accessed after including the following
line in the local 'cds.lib' file.

'DEFINE CBlib065oa /usr/local-eit/cad2/cadence/CBlib065oa'

Design Rule Check

It is possible to verify that the layout rules are not violated in the design. This is done by the
tool Calibre from Mentor Graphics. It is started from the Calibre menu in the layout
window, Calibre > Run nmDRC > Run DK DRC.

Two new windows are created. In the one labeled Customization Settingssome switches that affect the
checking can be modified. From the other, Calibre Interactive, the drc run can be started. The
errors are then presented in an easy to use viewer.

Calibre LVS

LVS, is the procedure where the layout is compared to the schematic drawing to detect discrepancies
in size, connections, etc. Calibre > Run nmLVS will activate the program for this task.

Global power nets, like vdd! and gnd!, will confuse Calibre and will be reported as wrong.

Select the button Ingore layout and source ports ... at Setup > LVS Options : Supply to avoid
the problem with the global supply nets.

Calibre PEX

The Parasitic EXtraction, Calibre > Run PEX, will calculate the parasitic components in the layout and
create a special view that can be simulated in order to gauge their impact on the design.

Select CALIBREVIEW and Names From LAYOUT at Outputs.The type of extraction can also be
chosen here.

At the end, when the Calibre View Setupwindow pops up, it is important to select Schematic as the
Calibre View Type.

The resulting view (calibre) can then be used by a config test bench as usual.