STMicroelectronics 65nm CMOS SOI v4.2

[Oct 2011]

This is the new design kit for the STM 65nm SOI cmos process.

It is restricted to those who have access to the 'radiocad' machine.

This page contains instructions on how to use the kit together with the analog
design tools on the Linux platform. If the need arises it will also be possible
to use the design kit together with the  digital tools.


Notes




Setup procedure

The environment is defined by a setup script which is called by the command

> source /home/radiocad/cmp/c65soi42/setup


The first time this is run, the script will also copy some files that are necessary for proper
function of the design kit. Afterwards the Cadence design tool can be started by

> icfb &


Connect new libraries to technology cmos065_soi .

Simulation is a little more complicated than usual. Start the procedure
by the command Tools > Setup Corners from the Analog Environment
window. Here, the wanted model files can be selected. After the selection
has been confirmed by Save Model File the simulation can be run
normally. See more in the documentation!


Documentation

There is also an extensive set of maunuals which can be read by a browser which
is started by the command

> unidoc &


I hope that what is below is correct!! If not, let me know!


Design Rule Check

It is now possible to verify that the layout rules for the design are fulfilled. This is done
by the tool Calibre from Mentor Graphics. It is started from the Calibre menu  header
in the layout window. If this does not exist, try removing the local .cdsinit file and redo
the initialization procedure where an new file wiil be created.

After selecting Run DRC in the Calibre menu two new windows are created. In the one
labeled Customer Settings some switches that affect the checking can be modified. From
the other, Calibre Interactive, the drc run can be started with the button Run DRC. The
errors are then presented in an easy to use viewer.


Calibre LVS

Calibre > Run LVS will start Calibre for a Layout versus Schematic check.  Here a
netlist created from the schematic view will be compared to an extracted netlist from the
layout. All component sizes and connections will be compared and discrepancies reported.

Under Rules check that $U2DK_CALIBRE_LVS_DECK is filled in. At Inputs infor-
mation of the cell to be tested can be found.

Run LVS will start the check.

Global power nets, like vdd!, will confuse Calibre and will be reported as wrong.

Select the button Ingore layout and source pins ... at LVS Options : Supply to avoid
the problem with the global supply nets.

Calibre PEX

The Parasitic EXtraction will calculate the parasitic components on the layout and
create a 'calibre' view that can be simulated in order to gauge their impact on the design.

Select CALIBREVIEW and Names From LAYOUT at Outputs. The type of extraction
(R, L, C) can also be chosen here.

The resulting view (calibre) can then be used by a config test bench as usual.