STMicroelectronics CMOS28 FDSOI v1.5.a Design Kit



Since Oct 2021 this is the newest version of the design kit for this process.
It should be used for all fabrication designs in the future.

As usual it is only available on the secret "radiocad" cluster of machines de-
dicated to this process.

For design with the synthesis tool from Synopsys look here.


Notes



Setup procedure

The environment is defined by a setup script which is called by the command

> source /usr/hidden/cmp/s28v15a/setup

The first time this is run, the script will also copy some files that are necessary for
proper operation. Afterwards the Cadence design tool can be started by

> virtuoso &

Connect new libraries to technology cmos32lp.


The home-made pad library, LU_PADS_8M, should be included from the start, otherwise
add the following line to the local cds.lib file.

DEFINE LU_PADS_8M /usr/hidden/cmp/LU_PADS_8M

Documentation

There is also an extensive set of maunuals which can be read by the web browser by the command

> firefox -no-remote $PDKITROOT/doc/html/index.html

Simulation

Use Launch > ADE L to start the Simulation environment.

Make sure that your local 'corners.scs' file is filled in at Model File, (Setup > Model Libraries), .

DRC and LVS

The environment for these programs are already in place. Remenber the Antenna check
for the design.

For LVS to work properly use the layers Mn label when creating the labes in the layout.

Here is a file listing some errors that are acceptable since they will be fixed by tiling etc.

Parasitic Extraction

In order to extract the parasitic components in the design a procedure that uses both
Calibre LVSand Cadence QRC is used. It is shortly described in the two files
$PDKITROOT/DATA/LVS/MGC/CALIBRE/README, section 3 and
$PDKITROOT/DATA/PEX/CDS/EXT/README, sec 1 and 2.


Here is an example on how to run for a design called smgate in the library smlibb.
The commands must be executed in the same vindow from which Cadence was started
and in the same library. Some steps described in the above files have been omitted
since they are not required.

Use Calibre to create a database, svdb.

Start by copying the file $DKITROOT/DATA/LVS/MGC/CALIBRE/cfg/LVS_pex.ctrl to the
current library. Execute the following commands to replace the names in that file with
your own.

sed -i "s|myCell.gds|lvsRunDir/smgate.calibre.db|g" LVS_pex.ctrl
sed -i "s|myCell.cdl|lvsRunDir/smgate.src.net|g" LVS_pex.ctrl
sed -i "s|myCell|smgate|g" LVS_pex.ctrl

And tell Calibre to run the command file

calibre -hier -lvs LVS_pex.ctrl >& lvs_qrc.log

Convert this database with Calibre.

Copy $DKITROOT/DATA/LVS/MGC/CALIBRE/cfg/calibreQRC.query.ctrl

Change the cellname

sed -i "s|myCell|smgate|g" calibreQRC.query.ctrl

And execute

calibre -query svdb < calibreQRC.query.ctrl >& calibre_ci.log

Let Cadence QRC do the final extraction.

Copy $DKITROOT/DATA/PEX/CDS/EXT/qrc.ccl to your local directory.

sed -i "s|EXT_TYPE|c_only_decoupled|g" qrc.ccl
sed -i "s|myCell|smgate|g" qrc.ccl
sed -i "s|CORNER|nominal|g" qrc.ccl
sed -i "s|##EXT_V##||g" qrc.ccl
sed -i "s|cdl_out_run_dir|./lvsRunDir|g" qrc.ccl
sed -i "s|myLib|smlibb|g" qrc.ccl
sed -i "s|##C_QRC##||g" qrc.ccl

Type of extraction: r_only, rc_coupled, rc_decoupled, c_only_coupled, c_only_decoupled

Extraction corner: FuncCmax, FuncCmin, FuncRCmax, FuncRCmin, SigCmax, SigCmin, SigRCmax,
SigRCmin, nominal

qrc -cmd qrc.ccl >& qrc.log

There should now be an c_av_extracted view of the cell in your library. This can
be used in a config schematic as usual.

Tiling

For the tiling step follow the procedure described in the file

$PDKITROOT/DATA/SMART_TILING/CALIBRE/README

The required variables are already set.

> calibre -gui -drc -runset $MGC_CALIBRE_SMART_TILING_RUNSET_FILE

The layout can be generated or picked from earlier drc runs.

Put the name of the design at Top Cell.

This will generate two stream files; <cell>_TILES.BE and <cell>_TILES.FE which can be read into a new library and instanciated in the design.