AMI Semiconductor v2004.02 

This page was updated im April 2008. Here is the Old AMIS page.

For this 0.35um CMOS process there is a set of libraries containing standard cells and
input/output pads. These can be used for design synthesis, functional verification, and
final floorplanning with a set of tools that is available.

The tools are briefly described below. For more complete instructions, tutorials etc look
in the information for the course in which this process is used.

Setup

All the tools needed are initialized by one command which should be run in an empty  sub-
directory. A lot of setup and example files will be created if they do not already exist. On
the department's computors the following command shall be used.

> source /usr/local-tde/cad1/europrac/dk16/allsetup

This stuff is also available on the laboratory machines on the efd-system, in which case
the command

> inittde digp2008             must be executed.



The setup routine will create a file structure like this

                                             StartDir
       ______________________|___________________
       |                    |                      |                     |                |
    vhdl          netlists          WORK          work          soc

Use StartDir as default location when running Synopsys or ModelSim. Before using the
Encounter tool, descend into the library soc. The function of the other directories are


Synthesis with Synopsys


The cell libraries available are

MTC45000 : Standard Cells. MTC45000.pdf
MTC45100 :
I/O Pads.           MTC45100.pdf


The synthesis program is started by the command  design_vision .

There is a small example that can be studied. Use 'source comp.dv' to start.


Simulation

Simulation is performed in the ModelSim v6.2 tool, which can handle both vhdl and verilog
files. Simulation can be executed before or after synthesis. The simulator tool is started by the
command 'vsim'.

There is a small example command file that runs through an entire simulation. This is executed
by typing 'vsim -do medfilt.cmd' at the shell prompt.

There is a lot of documentation available from the tool menues. Here is a direct address to a
tutorial  $MODEL_SIM/docs/pdfdocs/modelsim_se_tut.pdf


Place'n'Route

The place-and-route of the construction is performed by the Cadence tool Encounter.

It is started with the command 'encounter'.  Do not use an ampersand (&) here.  The window
from which Encounter is started will serve as the command input window.

The setup command will copy some setup- and command files that executes an example design
in Encounter. The entire  session is then launched by the command 'source MedFilt.com' from
the command window. Naturally the commands are also available from the tool menues.

As shown in the example pad placement file 'MedFilt.io' the corner- and power pads can be in-
troduced in this file. There is no need to edit them into the verilog file.

When the design is ready, it has to be saved in a special format (stream) before it is sent for
fabrication.  Invoke the command Design > Save > GDS  and fill in the names of the stream file
to be created and of the mapfile, amis_soc.map.